This invention relates to high voltage semiconductor devices and methods of fabrication.
A need presently exists for integrated arrays of high voltage devices such as in telephone crosspoint switching. Because of the high bias applied to such devices, which can range from 60-600 volts, design and fabrication presents special problems. Such high voltage devices in general require large distances between regions in order to keep the high electric fields generated during operation below the breakdown level, and therefore tend to be too expensive for widespread use. It is therefore desirable to produce devices which are more compact. In addition, certain geometries such as those found in bilateral transistors and field controlled diodes require isolation of special portions of the device in order to function at high voltages. At present, no adequate means of fabricating such devices exists.
A further problem which exists in the fabrication of arrays is obtaining dielectrically isolated wafers. Most prior art techniques utilize a thick layer of polycrystalline silicon as the substrate. Such a substrate is fragile, and in addition can cause a non-uniform wafer surface when the wafer is ground to its final thickness.
It is therefore a primary object of the invention to produce monolithic arrays of high voltage devices which are compact and uniform from device to device. It is a furthe object of the invention to provide a planar technology for fabricating such arrays in a reliable, reproducible fashion.